1. Technical Field
The present disclosure relates to the field of so-called three-dimensional integrated circuits, comprising a superposition of chips and other elements to provide interconnections and increase the integration density.
2. Description of the Related Art
FIG. 1 shows an example of such a three-dimensional structure, intended to connect one or several semiconductor chips containing integrated circuits to a printed circuit board.
In this example, two integrated circuit chips 1 and 2 assembled with an interposer 4 on a support 6, such as a ceramic, a polymer, a portion of printed circuit board or the like, are shown. The lower surface of support 6 supports connection elements, such as bumps 8, intended to provide a connection with a step between them compatible with the size and the location of the connection areas of a printed circuit board, not shown, on which the component must be assembled and to which it must be connected.
Each chip 1, 2 comprises, on its lower surface, an interconnection network formed of several metallization levels intended to connect points of the chip surface together and to pads located on the last metallization level. Each of these pads is connected by connection means such as metal pillars 10, for example, made of copper, to similar pads of the upper surface of an intermediate plate or interposer 4 having its upper and lower surfaces generally covered with an interconnection network. Interposer plate 4 comprises through vias 12, each of which is connected to one of the pads of the upper surface of this plate and to a pad of the lower surface of this plate, to redistribute the connections with the narrow step between connection elements 10 towards other connection elements 14 on the lower surface side of plate 4 with a wider step adapted to the possible step of the connections on support 6. Support 6 also comprises interconnection networks 16, 17 on its upper and lower surfaces, respectively, the pads of interconnection network 16 being connected to connection elements such as pillars 14 and the pads of interconnection network 17 being connected to pads for receiving bumps 8.
Many variations of such a structure are possible. For example, one or several chips may be provided instead of two integrated circuit chips 1 and 2. In one embodiment, at least one chip is used as a support for one or more other integrated circuit chips.
A difficulty with such assemblies is a possible lack of reliability over time. Indeed, support 6 and interposer plate 4, the latter being generally made of silicon, have different expansion coefficients. Thus, when this assembly is heated, lateral stress is exerted on connection elements 14 of interconnection network 16, whereby these elements or the weldings connecting them to the support and to the interposer plate risk cracking and altering the quality of the connections.
It is desirable to improve reliability of existing three-dimensional structures.